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High Voltage Latch-Up Proof, Quad SPST Switches ADG5412/ADG5413
FEATURES
Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (<10 ) 9 V to 22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at 15 V, 20 V, +12 V, and +36 V VSS to VDD analog signal range
FUNCTIONAL BLOCK DIAGRAMS
S1 IN1 D1 S2 IN2 D2 IN2 D2 IN1 D1 S2 S1
ADG5412
S3 IN3 IN3 D3 S4 IN4 D4 IN4
ADG5413
S3
APPLICATIONS
Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems
D3 S4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
GENERAL DESCRIPTION
The ADG5412/ADG5413 contain four independent singlepole/single-throw (SPST) switches. The ADG5412 switches turn on with Logic 1. The ADG5413 has two switches with digital control logic similar to that of the ADG5412; however, the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG5412 and ADG5413 do not have a VL pin. The digital inputs are compatible with 3 V logic inputs over the full operating supply range. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the devices suitable for video signal switching. The ADG5413
exhibits break-before-make switching action for use in multiplexer applications.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5412/ADG5413 can be operated from dual supplies up to 22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5412/ADG5413 can be operated from a single rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required.
2. 3.
4.
5. 6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
09202-001
D4
ADG5412/ADG5413 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 20 V Dual Supply ....................................................................... 4 12 V Single Supply ........................................................................ 5 36 V Single Supply ........................................................................ 6 Continuous Current per Channel, Sx or Dx ..............................7 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Typical Performance Characteristics ........................................... 10 Test Circuits ..................................................................................... 14 Terminology .................................................................................... 16 Trench Isolation .............................................................................. 17 Applications Information .............................................................. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5412/ADG5413 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C VDD to VSS 9.8 11 0.35 0.7 1.2 1.6 0.05 0.25 0.05 0.25 0.1 0.4 0.75 3.5 14 16 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ
Rev. 0 | Page 3 of 20
Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 10 V, IS = -10 mA; see Figure 24 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA
0.9 2
1.1 2.2
VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = m 10 V; see Figure 27 VS = 10 V, VD = m 10 V; see Figure 27 VS = VD = 10 V; see Figure 23
Drain Off Leakage, ID (Off )
0.75 2
3.5 12 2.0 0.8
Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5413 Only) Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On)
0.002 0.1 2.5 170 202 120 145 15
VIN = VGND or VDD
236 170
262 182
RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 25 RL = 1 k, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 , CL = 5 pF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz
6 240 -78 -70 0.009 167 -0.7 18 18 60
ADG5412/ADG5413
Parameter POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C 45 55 0.001
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max V min/V max
Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
70 1 9/22
Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = -20 V 10%, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C VDD to VSS 9 10 0.35 0.7 1.5 1.8 0.05 0.25 0.05 0.25 0.1 0.4 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5413 Only) 0.75 3.5 13 15 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ
Rev. 0 | Page 4 of 20
Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 15 V, IS = -10 mA; see Figure 24 VDD = +18 V, VSS = -18 V VS = 15 V, IS = -10 mA
0.9 2.2
1.1 2.5
VS = 15 V, IS = -10 mA VDD = +22 V, VSS = -22 V VS = 15 V, VD = m 15 V; see Figure 27 VS = 15 V, VD = m 15 V; see Figure 27 VS = VD = 15 V; see Figure 23
Drain Off Leakage, ID (Off )
0.75
3.5
Channel On Leakage, ID (On), IS (On)
2
12 2.0 0.8
0.002 0.1 2.5 158 187 110 138 12
VIN = VGND or VDD
217 154
240 170
RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 25
5 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk 310 -78 -70
ADG5412/ADG5413
Parameter Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C 0.007 160 -0.6 17 17 60 50 70 0.001
-40C to +85C
-40C to +125C
Unit % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ V min/V max
Test Conditions/Comments RL = 1 k, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 , CL = 5 pF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = -22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
110 9/22
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD 19 22 0.4 0.8 4.4 5.5 0.05 0.25 0.05 0.25 0.1 0.4 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF 0.75 3.5 27 31 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 10 V, IS = -10 mA; see Figure 24 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA
1 6.5
1.2 7.5
VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = VD = 1 V/10 V; see Figure 23
Drain Off Leakage, ID (Off )
0.75
3.5
Channel On Leakage, ID (On), IS (On)
2
12 2.0 0.8
0.002 0.1 2.5 225 296 150 187
VIN = VGND or VDD
358 222
403 247
RL = 300 , CL = 35 pF VS = 8 V; see Figure 31 RL = 300 , CL = 35 pF VS = 8 V; see Figure 31
Rev. 0 | Page 5 of 20
ADG5412/ADG5413
Parameter Break-Before-Make Time Delay, tD (ADG5413 Only) Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD VDD
1
25C 70
-40C to +85C
-40C to +125C
Unit ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/V max
Test Conditions/Comments RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 25 RL = 1 k, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 , CL = 5 pF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
38 95 -78 -70 0.07 180 -1.3 22 22 58 40 65 9/40
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD 10.6 12 0.35 0.7 2.7 3.2 0.05 0.25 0.05 0.25 0.1 0.4 0.75 3.5 15 17 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 30 V, IS = -10 mA; see Figure 24 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = -10 mA
0.9 3.8
1.1 4.5
VS = 0 V to 30 V, IS = -10 mA VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 27 VS = 1 V/30 V, VD = 30 V/1 V; see Figure 27 VS = VD = 1 V/30 V; see Figure 23
Drain Off Leakage, ID (Off )
0.75
3.5
Channel On Leakage, ID (On), IS (On)
2
12
Rev. 0 | Page 6 of 20
ADG5412/ADG5413
Parameter DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5413 Only) Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD VDD
1
25C
-40C to +85C
-40C to +125C 2.0 0.8
Unit V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/V max
Test Conditions/Comments
0.002 0.1 2.5 180 220 130 169 25
VIN = VGND or VDD
230 167
248 174
RL = 300 , CL = 35 pF VS = 18 V; see Figure 31 RL = 300 , CL = 35 pF VS = 18 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 18 V; see Figure 30 VS = 18 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 25 RL = 1 k, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 , CL = 5 pF; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
8 280 -78 -70 0.03 174 -0.8 18 18 58 80 100
130 9/40
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = -15 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = +20 V, VSS = -20 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 36 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
89 160 95 170 61 110 80 144
59 94 63 98 43 70 54 87
37 49 39 50 29 42 35 47
mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum
Rev. 0 | Page 7 of 20
ADG5412/ADG5413 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, JA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free
1
Rating 48 V -0.3 V to +48 V +0.3 V to -48 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 278 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 112.6C/W 30.4C/W 260(+0/-5)C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5.
Rev. 0 | Page 8 of 20
ADG5412/ADG5413 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
15 IN1 16 D1 14 IN2
IN1 1 D1 2 S1 3 VSS 4 GND 5
16 15
IN2 D2 S2 VDD
S1 1 VSS 2 GND 3 S4 4
ADG5412/ ADG5413
14 13
PIN 1 INDICATOR
13 D2
12 S2 11 VDD 10 NC 9 S3
TOP VIEW 12 NC (Not to Scale) S4 6 11 S3
10 9
ADG5412/ ADG5413
TOP VIEW (Not to Scale)
D4 7 IN4 8
D3
09202-002
NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT.
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 Exposed Pad Description Logic Control Input 1. Drain Terminal 1. This pin can be an input or output. Source Terminal 1. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal 4. This pin can be an input or output. Drain Terminal 4. This pin can be an input or output. Logic Control Input 4. Logic Control Input 3. Drain Terminal 3. This pin can be an input or output. Source Terminal 3. This pin can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal 2. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Logic Control Input 2. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 8. ADG5412 Truth Table
INx 1 0 Switch Condition On Off
Table 9. ADG5413 Truth Table
INx 0 1 S1, S4 Off On S2, S3 On Off
Rev. 0 | Page 9 of 20
09202-003
NC = NO CONNECT
IN3 7
IN4 6
D3 8
D4 5
IN3
ADG5412/ADG5413 TYPICAL PERFORMANCE CHARACTERISTICS
16 TA = 25C 14 12 ON RESISTANCE ()
10
12
VDD = +10V VDD = +9V VSS = -10V VSS = -9V VDD = +11V VSS = -11V
TA = 25C 10 VDD = 32.4V VSS = 0V
ON RESISTANCE ()
VDD = 36V VSS = 0V 8
8 6 4 VDD10 +13.5V = VSS = -13.5V VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V
6
VDD = 39.6V VSS = 0V
4
2
2 0 -20
0
09202-034
-15
-10
-5
0
5
10
15
20
0
5
10
15
20
25
30
35
40
45
VS, VD (V)
VS, VD (V)
Figure 4. RON as a Function of VS, VD (Dual Supply)
12
VDD = +18V VSS = -18V
Figure 7. RON as a Function of VS, VD (Single Supply)
18 16 14
10
ON RESISTANCE ()
8
VDD = +20V VSS = -20V VDD = +22V VSS = -22V
ON RESISTANCE ()
12 10 8 6 4
TA = +125C TA = +85C TA = +25C TA = -40C
6
4
2 2
-20 -15 -10 -5 0 VS, VD (V) 5 10 15 20 25
09202-035
-5
0 VS, VD (V)
5
10
15
Figure 5. RON as a Function of VS, VD (Dual Supply)
25
TA = 25C VDD = +10V VSS = 0V VDD = 10.8V VSS = 0V
Figure 8. RON as a Function of VS (VD) for Different Temperatures, 15 V Dual Supply
16 14 12
ON RESISTANCE ()
20
VDD = +9V VSS = 0V
ON RESISTANCE ()
TA = +125C
15
VDD = 11V VSS = 0V VDD = 13.2V VSS = 0V
10 8 6 4
TA = +85C TA = +25C TA = -40C
10
VDD = 12V VSS = 0V
5
2
0
09202-032
0
2
4
6
8 VS, VD (V)
10
12
14
-5
0 VS, VD (V)
5
10
15
20
Figure 6. RON as a Function of VS, VD (Single Supply)
Figure 9. RON as a Function of VS (VD) for Different Temperatures, 20 V Dual Supply
Rev. 0 | Page 10 of 20
09202-041
VDD = +20V VSS = -20V 0 -20 -15 -10
09202-040
0 -25
TA = 25C
VDD = +15V VSS = -15V 0 -15 -10
09202-033
ADG5412/ADG5413
30 VDD = 12V VSS = 0V
0.8 0.6 VDD = +20V VSS = -20V VBIAS = +15V/-15V ID, IS (ON) + + ID, IS (ON) - - 0.4 IS (OFF) + - 0.2 0 ID (OFF) - +
25 ON RESISTANCE () TA = +125C 20 TA = +85C 15 TA = +25C TA = -40C
LEAKAGE CURRENT (nA)
10
-0.2 -0.4 IS (OFF) - + ID (OFF) + -
5
09202-042
0
2
4
6 VS, VD (V)
8
10
12
0
25
50
75
100
125
TEMPERATURE (C)
Figure 10. RON as a Function of VS (VD) for Different Temperatures, 12 V Single Supply
16 14 TA = +125C TA = +85C TA = +25C TA = -40C
LEAKAGE CURRENT (nA)
Figure 13. Leakage Currents vs. Temperature, 20 V Dual Supply
0.6
VDD = 12V VSS = 0V VBIAS = 1V/10V
ID, IS (ON) + +
12
ON RESISTANCE ()
0.4 ID, IS (ON) - - 0.2 IS (OFF) + - ID (OFF) - +
10 8 6 4 2 0
0 ID (OFF) + -
VDD = 36V VSS = 0V 0 5 10 15 20 VS, VD (V) 25 30 35 40
09202-043
0
25
50
75
100
125
TEMPERATURE (C)
Figure 11. RON as a Function of VS (VD) for Different Temperatures, 36 V Single Supply
0.8 VDD = +15V VSS = -15V VBIAS = +10V/-10V
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
0.8 0.6
LEAKAGE CURRENT (nA)
0.6
ID, IS (ON) + + ID, IS (ON) - -
VDD = 36V VSS = 0V VBIAS = 1V/30V
ID, IS (ON) + + ID, IS (ON) - -
LEAKAGE CURRENT (nA)
0.4 ID (OFF) - + 0.2
0.4 IS (OFF) + - 0.2
0 -0.2
IS (OFF) + -
0 ID (OFF) - + IS (OFF) - + ID (OFF) + -
09202-037
IS (OFF) - + -0.4 ID (OFF) + -
-0.2
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 12. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
09202-039
-0.4
-0.6
09202-036
-0.2
IS (OFF) - +
09202-038
0
-0.6
ADG5412/ADG5413
0 -10 -20
OFF ISOLATION (dB)
TA = 25C VDD = +15V VSS = -15V
0 -10 -20 -30
TA = 25C VDD = +15V VSS = -15V
-30 -40 -50 -60 -70 -80 -90
09202-025
ACPSRR (dB)
-40 -50 -60 -70 -80 -90
NO DECOUPLING CAPACITORS
DECOUPLING CAPACITORS
10k
100k
1M
10M
100M
1G
10k
100k FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency, 15 V Dual Supply
0 -10 -20 -30
CROSSTALK (dB)
0.10 0.09 0.08 0.07
Figure 19. ACPSRR vs. Frequency, 15 V Dual Supply
TA = 25C VDD = +15V VSS = -15V
LOAD = 1k TA = 25C VDD = 12V, VSS = 0V, VS = 6V p-p
THD + N (%)
-40 -50 -60 -70 -80 -90
09202-028
0.06 0.05 0.04 VDD = 36V, VSS = 0V, VS = 18V p-p 0.03 0.02 0.01 0 VDD = 15V, VSS = 15V, VS = 15V p-p VDD = 20V, VSS = 20V, VS = 20V p-p 0 5 10 FREQUENCY (MHz) 15 20
09202-027
09202-029
-100 10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency, 15 V Dual Supply
500 450 400
VDD = +20V VSS = -20V 0 -0.5 -1.0
INSERTION LOSS (dB)
Figure 20. THD + N vs. Frequency, 15 V Dual Supply
TA = 25C
TA = 25C VDD = +15V VSS = -15V
CHARGE INJECTION (pC)
350 300 250 200 150 100 50
-10
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5
VDD = +36V VSS = 0V
VDD = +15V VSS = -15V
VDD = +12V VSS = 0V
0
10 VS (V)
20
30
40
09202-030
0 -20
-5.0 1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 18. Charge Injection vs. Source Voltage
Figure 21. Bandwidth
Rev. 0 | Page 12 of 20
09202-026
-100 1k
-100 1k
ADG5412/ADG5413
350 300 250
tON (12V) tON (20V) tON (15V) tON (36V) tOFF (15V)
TIME (ns)
200 150
100 50
tOFF (36V)
tOFF (12V)
tOFF (20V)
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 22. tON, tOFF Times vs. Temperature
09202-031
0 -40
Rev. 0 | Page 13 of 20
ADG5412/ADG5413 TEST CIRCUITS
IS (OFF)
ID (ON)
ID (OFF) Sx Dx A VD
09202-015
A
09202-016
Sx VS
Dx
A
VD
VS
Figure 23. On Leakage
VDD
0.1F
Figure 27. Off Leakage
VSS
0.1F AUDIO PRECISION VDD
VSS
Sx
IDS
INx
RS
V1 Sx Dx
09202-014
VS V p-p
Dx
VIN
GND
RL 1k
VOUT
09202-024
VS
RON = V1/IDS
Figure 24. On Resistance
VDD 0.1F NETWORK ANALYZER VOUT RL 50 VSS 0.1F
Figure 28. THD + Noise
VDD
0.1F
VSS
0.1F NETWORK ANALYZER Sx
VDD S1
VSS
VDD
Dx
VSS
S2 VS GND
RL 50
50
INx Dx
VS VOUT
VIN
GND
RL 50
09202-021
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
INSERTION LOSS = 20 log
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 25. Channel-to-Channel Crosstalk
VDD 0.1F VSS 0.1F NETWORK ANALYZER Sx INx Dx VIN GND RL 50 50
Figure 29. Bandwidth
VDD
VSS
50 VS VOUT
OFF ISOLATION = 20 log
VS
Figure 26. Off Isolation
09202-020
VOUT
Rev. 0 | Page 14 of 20
09202-023
VOUT VS
ADG5412/ADG5413
VDD 0.1F VSS 0.1F VIN 0V 50% 50%
VS1 VS2
VDD S1 S2
VSS D1 D2 RL 300 CL 35pF VOUT2 RL 300 CL 35pF
VOUT1
VOUT1
90% 0V
90%
VOUT2 0V
90%
90%
IN1, IN2
ADG5413
GND
Figure 30. Break-Before-Make Time Delay, tD
VDD 0.1F VSS 0.1F VIN VDD Sx VS VSS Dx RL 300 GND VOUT CL 35pF VOUT
ADG5412
50%
50%
INx
90%
90%
09202-018
tON
tOFF
Figure 31. Switching Times
VDD VSS
VDD RS VS Sx
VSS Dx VOUT CL 1nF VOUT GND QINJ = CL x VOUT VOUT
09202-019
VIN
ADG5412
ON OFF
IN
Figure 32. Charge Injection
Rev. 0 | Page 15 of 20
09202-017
tD
tD
ADG5412/ADG5413 TERMINOLOGY
IDD IDD represents the positive supply current. ISS ISS represents the negative supply current. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. RON RON represents the difference between the RON of any two channels. RFLAT (ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN is the digital input capacitance. tON tON represents the delay between applying the digital control input and the output switching on. tOFF tOFF represents the delay between applying the digital control input and the output switching off. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.
Rev. 0 | Page 16 of 20
ADG5412/ADG5413 TRENCH ISOLATION
In the ADG5412 and ADG5413, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latchup proof switch.
NMOS PMOS
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER HANDLE WAFER
09202-022
Figure 33. Trench Isolation
Rev. 0 | Page 17 of 20
ADG5412/ADG5413 APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5412/ADG5413 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from 9 V to 22 V. The ADG5412/ADG5413 (as well as other select devices within the same family) achieve an 8 kV human body model ESD rating, which provides a robust solution eliminating the need for separate protect circuitry designs in some applications.
Rev. 0 | Page 18 of 20
ADG5412/ADG5413 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
PIN 1 INDICATOR
4.10 4.00 SQ 3.90 0.65 BSC
0.35 0.30 0.25
13 12 EXPOSED PAD 1 16
PIN 1 INDICATOR
4 9 8 5
2.70 2.60 SQ 2.50
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADG5412BRUZ ADG5412BRUZ-REEL7 ADG5412BCPZ-REEL7 ADG5413BRUZ ADG5413BRUZ-REEL7 ADG5413BCPZ-REEL7
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
012909-B
Package Option RU-16 RU-16 CP-16-17 RU-16 RU-16 CP-16-17
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADG5412/ADG5413 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09202-0-7/10(0)
Rev. 0 | Page 20 of 20

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